IDT707278L的技术资料
● 32K x 16 Bank-Switchable Dual-Ported SRAM Architecture
– Four independent 8K x 16 banks
– 512 Kilobit of memory on chip
● Fast asynchronous address-to-data access time: 15ns
● User-controlled input pins included for bank selects
● Independent port controls with asynchronous address &
data busses
● Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
● Interrupt flags with programmable masking
● Dual Chip Enables allow for depth expansion without
external logic
● UB and LB are available for x8 or x16 bus matching
● TTL-compatible, single 5V (±10%) power supply
● Available in a 100-pin Thin Quad Flatpack (14mm x 14mm
IDT707278L的技术参数：
|
Symbol |
Rating |
Commercial & Industrial |
Unit |
| VTERM(2) |
Terminal Voltage with Respect to GND |
-0.5 to +7.0 |
V |
| TBIAS | Temperature Under Bias |
-55 to +125 |
o C |
| TSTG | Storage Te mp e ra ture |
-65 to +150 |
o C |
| IOUT | DC Output Current |
50 |
mA |
IDT707278L的产品描述：
The IDT707278 is a high-speed 32K x 16 (512K bit) Bank-Switchable Dual-Ported SRAM organized into four independent 8K x 16 banks. The device has two independent ports with separate controls, addresses, and I/O pins for each port, allowing each port to asynchronously access any 8K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user,s control. Mailboxes are provided to allow inter-processor communications. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very ow standby power mode and allows fast depth expansion.
The IDT707278 offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).
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